Note: This unit version is currently under review and is subject to change!

ELEC3608: Computer Architecture (2014 - Semester 2)

Download UoS Outline

Unit: ELEC3608: Computer Architecture (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Senior
Faculty/School: School of Electrical and Information Engineering
Unit Coordinator/s: A/Prof Leong, Philip
Session options: Semester 2
Versions for this Unit:
Campus: Camperdown/Darlington
Pre-Requisites: ELEC2602. Basic knowledge of digital logic is required.
Brief Handbook Description: This unit of study explores the design of a computer system at the architectural and digital logic level. Topics covered include instruction sets, computer arithmetic, performance evaluation, datapath design, pipelining, memory hierarchies including caches and virtual memory, I/O devices, and bus-based I/O systems. Students will design a pipelined reduced instruction set processor.
Assumed Knowledge: ELEC3607. Basic knowledge of assembly language and microprocessor systems is required.
Timetable: ELEC3608 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 2.00 1 12
2 Tutorial 2.00 1 12
3 Project Work - own time 4.00 1 3
T&L Activities: Laboratory: Laboratory experiments to revise concepts and gain familiarity with design tools.

Tutorial: Reinforce concepts and provide design examples of materials covered in lectures.

Independent Study: Self study

Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.

Attribute Development Method Attribute Developed
Students will be required to understand different computer architectures. They will be required to develop the skills needed to construct and simulate their own designs. Design (Level 2)
Students will need to develop skills required to consider different design choices. Engineering/IT Specialisation (Level 3)
Analytic skills for comparing design choices will be developed. Maths/Science Methods and Tools (Level 3)
Students will develop skills of collecting information from different sources and critically evaluating them. Information Seeking (Level 2)
Students will develop written communications skills through their tutorials and assignment. Communication (Level 2)
Students will be asked to reflect on management and business issues concerning this field.

Students will tackle a design project in teams, gaining project management skills in the process.
Professional Conduct (Level 2)
Students will tackle a design project in teams, gaining project management skills in the process. Project Management and Team Skills (Level 2)

For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

Design (Level 2)
1. Students will understand how to design a pipelined RISC processor with memory hierarchy.
Engineering/IT Specialisation (Level 3)
2. Students will be able to critically evaluate different pipelining schemes, memory designs and instruction sets.
Maths/Science Methods and Tools (Level 3)
3. Students will be able to model and benchmark the performance of different computer architectures.
Information Seeking (Level 2)
4. Students will be able to understand the literature in computer architecture design.
Communication (Level 2)
5. Students will further develop their communication skills through the assignment.
Professional Conduct (Level 2)
6. Students will learn how economic issues affect computer designers.
Project Management and Team Skills (Level 2)
7. Students will be given the opportunity to work in teams through assignments and deal with project managements issues of completing a design exercise.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Tutorial 1 Yes 2.00 Week 3 1, 2, 6,
2 Tutorial 2 Yes 2.00 Week 4 1, 2, 3, 4,
3 Tutorial 3 Yes 2.00 Week 5 1, 2, 3, 4,
4 Tutorial 4 Yes 2.00 Week 6 1, 2, 3, 4,
5 Tutorial 5 Yes 2.00 Week 7 1, 2, 3, 4,
6 Design exercise Yes 30.00 Week 12 1, 2, 5, 7,
7 Final exam No 60.00 Exam Period
Assessment Description: Tutorials: Cover basic theory for course.

Assignment: Design project.

Final Exam: 2 hour closed book.
Policies & Procedures: See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.
Prescribed Text/s: Note: Students are expected to have a personal copy of all books listed.
  • Computer Organization and Design

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Lecture: Computer abstractions and technology
Week 2 Lecture/Tutorial: Instruction sets
Week 3 Lecture/Tutorial: Computer arithmetic
Assessment Due: Tutorial 1
Week 4 Lecture/Tutorial: Computer arithmetic
Assessment Due: Tutorial 2
Week 5 Lecture/Tutorial: Processor design
Assessment Due: Tutorial 3
Week 6 Lecture/Tutorial: Processor design
Assessment Due: Tutorial 4
Week 7 Lecture/Tutorial: Processor design (pipelining)
Assessment Due: Tutorial 5
Week 8 Lecture/Tutorial: Processor design (pipelining)
Week 9 Lecture/Tutorial: Memory hierarchy
Week 10 Lecture/Tutorial: Memory hierarchy
Week 11 Lecture/Tutorial: Storage and I/O
Week 12 Storage and I/O
Assessment Due: Design exercise
Week 13 Lecture/Tutorial: Multicores, Multiprocessors and Clusters
Exam Period Assessment Due: Final exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Electrical (Computer) 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Arts 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Commerce 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Medical Science 2011, 2013, 2014
Electrical Engineering (Computer) / Science 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Law 2013, 2014
Electrical 2011, 2012, 2013, 2014
Electrical Engineering / Arts 2011, 2012, 2013, 2014
Electrical Engineering / Commerce 2010, 2011, 2012, 2013, 2014
Electrical Engineering (Bioelectronics) / Arts 2011, 2012
Electrical Engineering (Bioelectronics) / Science 2011, 2012
Electrical Engineering / Medical Science 2011, 2012, 2013, 2014
Electrical Engineering / Project Management 2012, 2013, 2014
Electrical Engineering / Science 2011, 2012, 2013, 2014
Electrical (Power) 2014
Electrical (Telecommunications) 2012, 2013, 2014
Electrical Engineering (Telecommunications) / Science 2011, 2012, 2013, 2014
Electrical Engineering (Power) / Project Management 2012, 2013, 2014
Electrical Engineering (Telecommunications) / Arts 2011, 2012, 2013, 2014
Electrical Engineering (Telecommunications) / Medical Science 2011, 2012, 2013, 2014

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
Design (Level 2) Yes 9.2%
Engineering/IT Specialisation (Level 3) Yes 12.2%
Maths/Science Methods and Tools (Level 3) Yes 1.6%
Information Seeking (Level 2) Yes 1.6%
Communication (Level 2) Yes 6%
Professional Conduct (Level 2) Yes 0.4%
Project Management and Team Skills (Level 2) Yes 9%

These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.