ELEC5722: Foundations of Digital Systems Design (2014 - Semester 1)

Download UoS Outline

Unit: ELEC5722: Foundations of Digital Systems Design (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Postgraduate
Faculty/School: School of Electrical & Information Engineering
Unit Coordinator/s: Dr McEwan, Alistair
Session options: Semester 1
Versions for this Unit:
Site(s) for this Unit: https://elearning.sydney.edu.au/
Campus: Camperdown/Darlington
Pre-Requisites: None.
Brief Handbook Description: The purpose of this unit is to equip the students with the skills to design simple digital logic circuits which comprise modules of larger digital systems.

The following topics are covered: logic operations, theorems and Boolean algebra, number operations (binary, hex, integer and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, and the design of a simple computer.
Assumed Knowledge: This unit of study assumes some knowledge of digital data representation and basic computer organisation.
Lecturer/s: Thomas, Charles
Tutor/s: Michael Frechtling, Mahendra Samarawickrama, Daniel Shan
Timetable: ELEC5722 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 2.00 1 13
2 Laboratory 3.00 1 10
3 Independent Study 2.00 1 13
4 Tutorial 2.00 1 13
5 Laboratory pre-work 2.00 1 10
T&L Activities: Laboratory: Laboratory experiments

Independent Study: Self study

Tutorial: Home work

Laboratory: Prelab work

Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.

Attribute Development Method Attribute Developed
The design problems are discussed during lectures Design (Level 3)
Apply basic design techniques grounded in digital electronics Engineering/IT Specialisation (Level 3)
Ability to apply the basic principles of digital electronics in analysing and designing digital circuits and systems Maths/Science Methods and Tools (Level 3)
Extensive use of Information Literacy Tools and Techniques during Laboratory. Information Seeking (Level 2)
Group work in Laboratory and also interaction during lectures. Communication (Level 2)
Group work in Laboratory and well as interaction during lectures. Project and Team Skills (Level 1)

For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

Design (Level 3)
1. Ability to undertake design of combinational logic circuits.
2. Ability to undertake design with multiplexers, decoders, and PLAs.
3. Ability to design sequential circuits using state graphs and state tables.
4. Ability to design combinational and sequential circuits and systems, using a clearly defined system based approach.
Engineering/IT Specialisation (Level 3)
5. Ability to demonstrate understanding of latches, flip-flops, registers and counters to the extent of the course material.
6. Ability to perform analysis of clocked sequential circuits.
Maths/Science Methods and Tools (Level 3)
7. Ability to demonstrate understanding of Boolean algebra for the purpose of logic circuits analysis.
Information Seeking (Level 2)
8. Able to use Information Literacy Tools and Techniques extensively during Laboratory.
Communication (Level 2)
9. Ability to communicate effectively among the team members of the group to design, fabricate and test the digital circuits and system in the laboratory
Project and Team Skills (Level 1)
10. Ability to work in groups by assuming diverse team roles, taking on shared responsibilities and demonstrating an openness to different perspectives and an ability to reach consensus on specific engineering projects/tasks.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Lab Report Yes 20.00 Multiple Weeks 1, 2, 3, 4, 5, 6, 8, 9, 10,
2 Assignment No 10.00 Multiple Weeks 1, 2, 3, 4, 5, 6, 7,
3 Final Exam No 70.00 Exam Period 1, 2, 3, 4, 5, 6, 7,
Assessment Description: Lab Work: 6 lab sessions plus 3 lab reports.

Assignment/Lab Project: Group project running over three weeks with individual reports to submit at the end.

Final Exam: Two Hours
Grading:
Grade Type Description
Standards Based Assessment Final grades in this unit are awarded at levels of HD for High Distinction, DI (previously D) for Distinction, CR for Credit, PS (previously P) for Pass and FA (previously F) for Fail as defined by University of Sydney Assessment Policy. Details of the Assessment Policy are available on the Policies website at http://sydney.edu.au/policies . Standards for grades in individual assessment tasks and the summative method for obtaining a final mark in the unit will be set out in a marking guide supplied by the unit coordinator.
Policies & Procedures: See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.
Prescribed Text/s: Note: Students are expected to have a personal copy of all books listed.
Online Course Content: https://elearning.sydney.edu.au/

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Introduction:
Boolean Algebra
Reading: 2.1-2.5 (excluding 2.5.1)
Week 2 Reading: 2.8-2.10
Combinatorial circuits
VHDL
Week 3 VHDL continued
Reading: 6.1-6.3
Week 4 Implementing Boolean functions
Reading: 2.6-2.7
Week 5 Reading: 7.1-7.5
Flip-flops and latches
Week 6 Flip-flops and latches
Reading: 7.1-7.5
Week 7 Sequential circuit design
Reading: 8.1,8.2,8.4.1,8.4.4,8.4.5,Example 8.6,8.7.1-8.7.4,Figure 7.62,6.6.4
Week 8 Arithmetic circuits
Reading: 5.1-5.3,5.7.1-5.7.2
Week 9 A simple processor
Reading: 5.1-5.3,5.7.1-5.7.2
Week 10 Timing
Reading: 7.4.4,7.15
Week 11 Implementation technology
Reading: 3.1,3.3,3.5-3.7
Week 12 ASM Charts, Mealy Machines and Multipliers
Reading: 8.10,10.2.3
Week 13 Reconfigurable computing, revision
Reading: Appendix A
Exam Period Assessment Due: Final Exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Master of Professional Engineering (Electrical) 2013, 2014, 2015
Master of Professional Engineering (Power) 2013, 2014, 2015
Master of Professional Engineering (Software) 2013, 2014, 2015
Master of Professional Engineering (Telecommunications Engineering) 2013, 2014, 2015

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
Design (Level 3) Yes 54.62%
Engineering/IT Specialisation (Level 3) Yes 27.31%
Maths/Science Methods and Tools (Level 3) Yes 11.43%
Information Seeking (Level 2) Yes 2.22%
Communication (Level 2) Yes 2.22%
Professional Conduct (Level 1) No 0%
Project and Team Skills (Level 1) Yes 2.22%

These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.