Note: This unit version is currently being edited and is subject to change!
ELEC2602: Digital Logic (2016 - Semester 1)
|Unit:||ELEC2602: Digital Logic (6 CP)|
|Faculty/School:||School of Electrical & Information Engineering|
Dr Sathiakumar, Swamidoss
|Session options:||Semester 1|
|Versions for this Unit:|
|Site(s) for this Unit:||
|Brief Handbook Description:||The purpose of this unit is to equip students with the skills to design simple digital logic circuits which comprise modules of larger digital systems.
The following topics are covered: logic operations, theorems and Boolean algebra, number systems (integer and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, and the design of a simple computer.
|Assumed Knowledge:||ELEC1601. This unit of study assumes some knowledge of digital data representation and basic computer organisation.|
Dr Stepien, Peter
|Tutor/s:||To be advised.|
|T&L Activities:||Laboratory: Laboratory experiments.
Independent Study: Self study.
Tutorial: Home work.
Laboratory: Preparation for laboratory experiments.
Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.
|Attribute Development Method||Attribute Developed|
|The design problems are discussed during lectures||Design (Level 3)|
|Apply basic design techniques grounded in digital electronics||Engineering/IT Specialisation (Level 3)|
|Ability to apply the basic principles of digital electronics in analysing and designing digital circuits and systems||Maths/Science Methods and Tools (Level 3)|
|Extensive use of Information Literacy Tools and Techniques during Laboratory.||Information Seeking (Level 2)|
|Group work in Laboratory and also interaction during lectures.||Communication (Level 2)|
|Group work in Laboratory and well as interaction during lectures.||Project and Team Skills (Level 1)|
For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.
Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.Design (Level 3)
Short Quizzes: Total of 5 quizzes spread out over the semester. To be completed using Blackboard.
Lab Exercises: Total of 6 lab exercises, with 5 lab exercises assessed during lab sessions based on demonstrated work and written journal. Completed in groups and assessed individually.
Lab Project: Major project running over 3 weeks, assessed during lab sessions based on demonstrated work and written journal. A lab report will also be assessed. Completed in groups and assessed individually.
Final Exam: Two Hours during formal exam period.
|Policies & Procedures:||See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.|
Note: Students are expected to have a personal copy of all books listed.
|Online Course Content:||https://elearning.sydney.edu.au/|
Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp
|Week 1||Lecture: Introduction to Digital Logic|
|Reading: Chapter 2|
|Week 2||Lecture: VHDL and Implementing Logic Functions|
|Reading: Chapter 2, 4 and Appendix A|
|Week 3||Lecture: Combinational Building Blocks and VHDL|
|Reading: Chapter 6 Section 1 to 3|
|Week 4||Lecture: VHDL Building Blocks, Numbers and Adders|
|Reading: Chapter 5 Section 1, 2, 5, Chapter 6 Section 5|
|Week 5||Lecture: Comparators, Adders and Subtractors|
|Reading: Chapter 5 Section 1 to 3 and 5, Chapter 6 Section 5 and 6|
|Week 6||Lecture: Flip-Flops, Latches and Clocks|
|Reading: Chapter 7 Section 1 to 5, 10, 12|
|Week 7||Lecture: Registers and Counters|
|Reading: Chapter 7 Section 8 to 13|
|Week 8||Lecture: Finite State Machines|
|Reading: Chapter 8 Section 1 to 7|
|Week 9||Lecture: Datapaths and Control|
|Reading: Chapter 7 Section 14|
|Week 10||Lecture: Processors, Memory and Branching|
|Reading: Chapter 10 Section 2|
|Week 11||Lecture: Multipliers, Dividers and Timing|
|Reading: Chapter 10 Section 2 and 3, Chapter 10 Section 3 to 11|
|Week 12||Lecture: Metastability and Reconfigurable Logic|
|Reading: Chapter 3 Section 1 to 3, Chapter 10 Section 3|
|Week 13||Lecture: Synthesis, Testing and Exam Review|
|Reading: Chapter 11 and 12|
|Exam Period||Assessment Due: Final Exam|
The following is a list of courses which have added this Unit to their structure.
This unit contributes to the achievement of the following course goals:
|Design (Level 3)||Yes||54.62%|
|Engineering/IT Specialisation (Level 3)||Yes||27.31%|
|Maths/Science Methods and Tools (Level 3)||Yes||11.43%|
|Information Seeking (Level 2)||Yes||2.22%|
|Communication (Level 2)||Yes||2.22%|
|Professional Conduct (Level 1)||No||0%|
|Project and Team Skills (Level 1)||Yes||2.22%|
These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.