Note: This unit version is currently under review and is subject to change!
ELEC3607: Embedded Systems (2016 - Semester 1)
|Unit:||ELEC3607: Embedded Systems (6 CP)|
|Faculty/School:||School of Electrical & Information Engineering|
Prof Leong, Philip
|Session options:||Semester 1|
|Versions for this Unit:|
|Site(s) for this Unit:||
|Pre-Requisites:||ELEC1601 AND ELEC2602.|
|Brief Handbook Description:||Embedded systems have become pervasive in modern society. The aim of this unit of study is to teach students about embedded systems architecture, design methodology, interfacing and programming. Topics covered include peripheral devices, interrupts, direct memory access (DMA), assembly language, communications and data acquisition. A major design project is part of this course.|
|Assumed Knowledge:||ELEC1601 AND ELEC2602. Logic operations, theorems and Boolean algebra, data representation, number operations (binary, hex, integers and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, basic computer organisation, the CPU, peripheral devices, software organisation, machine language, assembly language, operating systems, data communications and computer networks.|
Mr Noorian, Farzad
|T&L Activities:||Laboratory: Laboratory exercises to re-enforce theory.
Independent Study: Prelab exercises and reading of text.
Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.
|Attribute Development Method||Attribute Developed|
|Laboratory exercises consist of design and problem solving.||Design (Level 3)|
|Expertise specific to microcomputers and digital systems.||Engineering/IT Specialisation (Level 3)|
|Development of fundamentals of microcomputers and projects.||Maths/Science Methods and Tools (Level 3)|
|Skill in accessing and handling information on microcomputers.||Information Seeking (Level 2)|
|Working in groups to solve design problems, report writing.||Communication (Level 3)|
|Development of professional practice in design projects.||Professional Conduct (Level 1)|
|Working in teams on design projects.||Project and Team Skills (Level 2)|
For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.
Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.Design (Level 3)
Final Exam: 2 hour exam. You must get 45% in the final exam to pass the unit, regardless of the sum of your individual marks.
Log Book: Log book kept on each laboratory exercise.
Assignment: Complete the design and implementation of an embedded system of the students' choosing, mutually agreed by the student and lecturer/tutors.
There may be statistically defensible moderation when combining the marks from each component to ensure consistency of marking between markers, and alignment of final grades with unit outcomes.
Penalties for late submissions will be 15% per day, rounded up to the nearest whole day.
* indicates an assessment task which must be repeated if a student misses it due to special consideration
|Policies & Procedures:||See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.|
Note: References are provided for guidance purposes only. Students are advised to consult these books in the university library. Purchase is not required.
|Library e-Reserve:||Please check the Library e-Reserve site for additional course resources.|
|Online Course Content:||https://flip.ee.usyd.edu.au/seiewiki/ELEC3607|
Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp
|Week 2||Independent study.|
|Laboratory exercise 1: General Purpose I/O.|
|Week 3||Laboratory exercise 2: Switch Debouncing and General Purpose I/O.|
|Week 4||Laboratory exercise 3: Counter/Timer.|
|Assessment Due: Assignment Milestone I*|
|Week 5||Laboratory exercise 4: UART and Interrupts.|
|Analog to digital converters and DMA|
|Week 6||Laboratory exercise 5: Power Supplies.|
|Finite state machines|
|Assessment Due: Assignment Milestone II*|
|Week 7||Independent study.|
|Week 8||Programming and debugging|
|Week 9||Independent study.|
|Week 10||Assignment 4.|
|Week 11||Assignment 5.|
|Week 12||Assembly language|
|Assessment Due: Assignment Milestone III*|
|Assessment Due: Assignment Milestone IV*|
|STUVAC (Week 14)||Independent study.|
|Exam Period||Final exam.|
|Assessment Due: Final Exam|
The following is a list of courses which have added this Unit to their structure.
This unit contributes to the achievement of the following course goals:
|Design (Level 3)||Yes||3.2%|
|Engineering/IT Specialisation (Level 3)||Yes||58.9%|
|Maths/Science Methods and Tools (Level 3)||Yes||20.7%|
|Information Seeking (Level 2)||Yes||0%|
|Communication (Level 3)||Yes||7.5%|
|Professional Conduct (Level 1)||Yes||0%|
|Project and Team Skills (Level 2)||Yes||9.7%|
These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.