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ELEC9602: Digital Logic (2019 - Semester 1)

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Unit: ELEC9602: Digital Logic (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Postgraduate
Faculty/School: School of Electrical & Information Engineering
Unit Coordinator/s: Dr Boland, David
Session options: Semester 1
Versions for this Unit:
Site(s) for this Unit: https://elearning.sydney.edu.au/
Campus: Camperdown/Darlington
Pre-Requisites: None.
Prohibitions: ELEC5722.
Brief Handbook Description: The purpose of this unit is to equip students with the skills to design simple digital logic circuits which comprise modules of larger digital systems.

The following topics are covered: logic operations, theorems and Boolean algebra, number systems (integer and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, and the design of a simple computer.
Assumed Knowledge: This unit of study assumes some knowledge of digital data representation and basic computer organisation.
Tutor/s: To be advised.
Timetable: ELEC9602 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 2.00 1 13
2 Laboratory 3.00 1 10
3 Independent Study 2.00 1 13
4 Tutorial 1.00 1 13
5 Laboratory Preparation 3.00 1 10
T&L Activities: Laboratory: Laboratory experiments.

Independent Study: Self study.

Tutorial: Home work.

Laboratory: Preparation for laboratory experiments

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

(6) Communication and Inquiry/ Research (Level 2)
1. Ability to communicate effectively among the team members of the group to design, fabricate and test the digital circuits and system in the laboratory
(7) Project and Team Skills (Level 1)
2. Ability to work in groups by assuming diverse team roles, taking on shared responsibilities and demonstrating an openness to different perspectives and an ability to reach consensus on specific engineering projects/tasks.
(4) Design (Level 3)
3. Ability to design combinational and sequential circuits and systems, using a clearly defined system based approach.
(2) Engineering/ IT Specialisation (Level 3)
4. Ability to undertake design of combinational logic circuits.
5. Ability to undertake design with multiplexers, decoders, and PLAs.
6. Ability to design sequential circuits using state graphs and state tables.
7. Ability to demonstrate understanding of latches, flip-flops, registers and counters to the extent of the course material.
8. Ability to perform analysis of clocked sequential circuits.
9. Ability to demonstrate understanding of Boolean algebra for the purpose of logic circuits analysis.
10. Able to use Information Literacy Tools and Techniques extensively during Laboratory.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Pre-lab Exercises No 5.00 Multiple Weeks 3, 4, 5, 6, 7, 8, 9,
2 Lab Exercises Yes 20.00 Multiple Weeks 1, 2, 3, 4, 5, 6, 7, 8, 10,
3 Lab Project Yes 15.00 Multiple Weeks 3, 4, 5, 6, 7, 8, 9,
4 Final Exam No 60.00 Exam Period 3, 4, 5, 6, 7, 8, 9,
Assessment Description: Pre-lab Exercises: Preparation exercises that must be completed in advance of specified lab sessions. Tutors will mark completion at beginning of your relevant timetabled lab session.

Lab Exercises: Total of 6 lab exercises, with 5 lab exercises assessed during lab sessions based on demonstrated work and understanding. Completed in groups and assessed individually.

Lab Project: Major project running over 3 weeks, assessed during lab sessions based on demonstrated work and lab report. Completed in groups and assessed individually.

Final Exam: Two Hours during formal exam period.

There may be statistically and educationally defensible methods used when combining the marks from each component to ensure consistency of marking between markers, and alignment of final grades with grade descriptors.

The University has authorised and mandated the use of text-based similarity detecting software Turnitin for all text-based written assignments

Lateness penalties:

Pre-lab exercises must be completed prior to attending the lab session. They will be marked by tutors within the first half hour of the lab session to account for late attendance. After this, no marks will be awarded under regular circumstances.

Lab project report: 10% penalty per day late
Grading:
Grade Type Description
Standards Based Assessment Final grades in this unit are awarded at levels of HD for High Distinction, DI (previously D) for Distinction, CR for Credit, PS (previously P) for Pass and FA (previously F) for Fail as defined by University of Sydney Assessment Policy. Details of the Assessment Policy are available on the Policies website at http://sydney.edu.au/policies . Standards for grades in individual assessment tasks and the summative method for obtaining a final mark in the unit will be set out in a marking guide supplied by the unit coordinator.
Policies & Procedures: See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.
Prescribed Text/s: Note: Students are expected to have a personal copy of all books listed.
Online Course Content: https://elearning.sydney.edu.au/

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Lecture: Introduction to Digital Logic
Reading: Chapter 2
Week 2 Lecture: VHDL and Implementing Logic Functions
Reading: Chapter 2, 4 and Appendix A
Week 3 Lecture: Combinational Building Blocks and VHDL
Reading: Chapter 6 Section 1 to 3
Week 4 Lecture: VHDL Building Blocks, Numbers and Adders
Reading: Chapter 5 Section 1, 2, 5, Chapter 6 Section 5
Week 5 Lecture: Comparators, Adders and Subtractors
Reading: Chapter 5 Section 1 to 3 and 5, Chapter 6 Section 5 and 6
Week 6 Lecture: Flip-Flops, Latches and Clocks
Reading: Chapter 7 Section 1 to 5, 10, 12
Week 7 Lecture: Registers and Counters
Reading: Chapter 7 Section 8 to 13
Week 8 Lecture: Finite State Machines
Reading: Chapter 8 Section 1 to 7
Week 9 Lecture: Datapaths and Control
Reading: Chapter 7 Section 14
Week 10 Lecture: Processors, Memory and Branching
Reading: Chapter 10 Section 2
Week 11 Lecture: Multipliers, Dividers and Timing
Reading: Chapter 10 Section 2 and 3, Chapter 10 Section 3 to 11
Week 12 Lecture: Metastability and Reconfigurable Logic
Reading: Chapter 3 Section 1 to 3, Chapter 10 Section 3
Week 13 Lecture: Synthesis, Testing and Exam Review
Reading: Chapter 11 and 12
Exam Period Assessment Due: Final Exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Master of Professional Engineering (Electrical) 2015, 2016, 2017, 2018, 2019, 2020
Master of Professional Engineering (Intelligent Information Engineering) 2020
Master of Professional Engineering (Power) 2015, 2016, 2017, 2018, 2019, 2020
Master of Professional Engineering (Software) 2015
Master of Professional Engineering (Telecommunications) 2015, 2016, 2017, 2018, 2019, 2020

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
(6) Communication and Inquiry/ Research (Level 2) No 2.22%
(7) Project and Team Skills (Level 1) No 2.22%
(8) Professional Effectiveness and Ethical Conduct (Level 1) No 0%
(5) Interdisciplinary, Inclusiveness, Influence (Level 3) No 0%
(4) Design (Level 3) No 13.65%
(2) Engineering/ IT Specialisation (Level 3) No 81.92%
(3) Problem Solving and Inventiveness (Level 3) No 0%
(1) Maths/ Science Methods and Tools (Level 3) No 0%

These goals are selected from Engineering & IT Graduate Outcomes Table 2018 which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table 2018 for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.