MTRX1702: Mechatronics 1 (2015 - Semester 2)
|Unit:||MTRX1702: Mechatronics 1 (6 CP)|
|Faculty/School:||School of Aerospace, Mechanical & Mechatronic Engineering|
A/Prof Rye, David
|Session options:||Semester 2|
|Versions for this Unit:|
|Site(s) for this Unit:|
|Prohibitions:||ELEC1101 OR ELEC2602 OR COSC1002 OR COSC1902.|
|Brief Handbook Description:||This unit of study aims to provide an introduction to the analysis and design of digital logic circuits and to provide a foundation for the study of systems and embedded programming for the degree in Mechatronic Engineering.
Introductory Digital Systems (3 CR): Number systems and codes; Logic gates and Boolean algebra, universal (NAND) logic gates; Digital arithmetic: operations and circuits, Two`s complement addition and subtraction, overflow; Combinational logic circuits; Flip-flops and related devices; Counters and registers, shift register applications; sequential circuits, designs of synchronous, cascadable counters (BCD and binary). Integrated circuit logic families and interfacing; practical issues including, fan out, pull-up/down, grounds, power supplies and decoupling; timing issues, race conditions. Tri-state signals and buses; MSI logic circuits, multiplexers, demultiplexers, decoders, magnitude comparators; Introduction to programmable logic devices. The unit of study will include a practical component where students design and implement logic circuits. Purchase of a basic laboratory tool kit as described in classes will be required.
Introductory Software Engineering (3 CR): This unit of study provides an introduction to software design, implementation, debugging and testing in the context of C programming language. Problem definition and decomposition; the design process; designing for testing and defensive coding methods; modular code structure and abstract data types; best practice in programming. Preprocessor, tokens, storage classes and types. Arithmetic, relational and bit manipulation operators. Constructs for control flow: if, switch, for, do and while. Arrays. Pointers and character strings. Dynamic memory. Functions and parameter passing. Derived storage classes: structures and unions. File I/O.
Dr Ward , James
Mounir Boudali, Tyrone Pollard, Bastiaan Uytterhoeven-Spark and Lloyd Windrim (Digital Systems)
Graeme Best and Joe Nguyen (Software Engineering)
|T&L Activities:||Tutorial: Laboratory-based electronics and programming tutorials.
Independent Study: Students are expected to undertake at least five hours of independent study per week outside of formally timetabled classes. Students are expected to commit to private study, which may include lab work, outside of the time tabled hours. It is expected that the appropriate reference books and web-based material will be read to supplement material presented during lectures.
Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.
|Attribute Development Method||Attribute Developed|
|Problem definition and analysis, systematic design, implementation and fault-finding in both hardware and software.||Design (Level 2)|
|Theoretical foundations of digital systems and software engineering.||Engineering/IT Specialisation (Level 2)|
For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.
Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.Design (Level 2)
Moderation of Group Work Marks Marks for team-based work may be moderated on the basis of individual effort and understanding as perceived by the lecturer and tutors.
Method of Submission of Assignments All work must be submitted electronically. You may hand-draw some material such as diagrams and scan or photograph them for insertion into electronic documents. Hand-drawn work that is illegible will not be assessed. Further information on the methods of submission will be given in class. A completed copy of the Compliance Statement must be incorporated in each assignment to certify that the assignment has been completed in accordance with the University`s policy on Academic Dishonesty & Plagiarism.
Late Submission of Assignments Late submissions will be penalized 20% of the full mark for every day or part thereof that the assignment is late.
Assignment Extensions and Deadlines No extension of the published due dates and times will be given unless exceptional circumstances apply. In such cases, application for an extension must be submitted in writing (e.g. by email to the component lecturer), citing those circumstances. A decision will be given in writing (email).
Must Pass Both Components To pass this unit of study it is necessary to obtain a mark of not less than 45% in BOTH the Digital Systems and Software Engineering components. If you fail either component the maximum mark you can get for the unit of study is 45%.
|Assessment Feedback:||Students can expect feedback for this Unit of Study through discussion during lectures and laboratory/project work sessions, and through written responses to questions posed via email. Students can provide feedback to the Lecturer and Tutors by discussion during lectures or tutorial/ laboratory sessions, and by submitting comments and questions by email.|
|Policies & Procedures:||See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.|
Note: References are provided for guidance purposes only. Students are advised to consult these books in the university library. Purchase is not required.
|Online Course Content:||via the University LMS (Blackboard)|
|Note on Resources:||Library classifications: 005.133, 621.3819, 621.39|
Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp
|Week 1||Software Engineering: Introduction|
|Digital Systems: Introduction|
|Week 2||Digital Systems: Basics of electrical circuits|
|Software Engineering: Data types|
|Week 3||Software Engineering: Arithmetic operations|
|Digital Systems: Basic logic operations|
|Week 4||Software Engineering: Decisions and loops|
|Digital Systems: Boolean algebra|
|Week 5||Digital Systems: Simplification of logic functions|
|Software Engineering: Functions|
|Assessment Due: Digital Systems Assignment 1|
|Week 6||Digital Systems: Transistors and basic logic families|
|Software Engineering: Scope and extent|
|Week 7||Digital Systems: Practical issues in digital circuits|
|Software Engineering: Pointers|
|Assessment Due: Software Engineering Assignment 1|
|Week 8||Software Engineering: Pointer arithmetic|
|Digital Systems: Sequential logic|
|Assessment Due: Digital Systems Assignment 2|
|Week 9||Digital Systems: Multiplexers, demultiplexers and other digital integrated circuits|
|Software Engineering: Arrays and strings|
|Week 10||Software Engineering: Bitwise operations|
|Digital Systems: Representation of signed numbers|
|Week 11||Software Engineering: Dynamic memory|
|Digital Systems: Design example|
|Week 12||Digital Systems: Complex design techniques|
|Software Engineering: The C preprocessor|
|Assessment Due: Software Engineering Assignment 2|
|Week 13||Digital Systems: Review and discussion|
|Software Engineering: User defined types|
|Assessment Due: Digital Systems Assignment 3|
|Exam Period||Assessment Due: Final Exam|
The following is a list of courses which have added this Unit to their structure.
This unit contributes to the achievement of the following course goals:
|Design (Level 2)||Yes||25%|
|Engineering/IT Specialisation (Level 2)||Yes||75%|
These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.