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MTRX1705: Introduction to Mechatronic Design (2019 - Semester 2)

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Unit: MTRX1705: Introduction to Mechatronic Design (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Junior
Faculty/School: School of Aerospace, Mechanical & Mechatronic Engineering
Unit Coordinator/s: Professor Nebot, Eduardo
Session options: Semester 2
Versions for this Unit:
Campus: Camperdown/Darlington
Pre-Requisites: None.
Brief Handbook Description: This unit of study aims to provide an introduction to the basic hardware elements of mechatronic systems.

Basic electrical theory: Ohms law, Kirchoff’s voltage and current laws, passive component characteristics (resistors, capacitors & inductors).

Number systems and codes; Logic gates and Boolean algebra, universal (NAND) logic gates; Digital arithmetic: operations and circuits, Two`s complement addition and subtraction, overflow; Combinational logic circuits; Flip-flops and related devices; Counters and registers, shift register applications; sequential circuits, designs of synchronous, cascadable counters (BCD and binary). Integrated circuit logic families and interfacing; practical issues including, fan out, pull-up/down, grounds, power supplies and decoupling; timing issues, race conditions. Tri-state signals and buses; MSI logic circuits, multiplexers, demultiplexers, decoders, magnitude comparators; Introduction to programmable logic devices.

Brushed DC Motors: Introduction to characteristics and control, motor specifications, torque-speed characteristics, power and efficiency, thermal considerations.

Introduction to BJTs and FETs as switches. PWM control of DC motors; half- and full-bridge configurations; Feedback and operational amplifiers; selected op-amp applications circuits with an emphasis on sensor and actuator interfacing.

The unit of study will include a practical component where students design and implement logic and linear circuits. Purchase of a basic laboratory tool kit as described in classes will be required.
Assumed Knowledge: None.
Lecturer/s: Dr Worrall, Stewart
Tutor/s: to be advised
Timetable: MTRX1705 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 2.00 2 13
2 Tutorial/Laboratoty 3.00 1 13
3 Independent Study 5.00

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

(4) Design (Level 2)
1. Ability to analyse and design combinational and sequential logic circuits from basic logic elements.
2. Ability to analyse and design applications circuits based on operational amplifiers.
(2) Engineering/ IT Specialisation (Level 2)
3. Ability to read and understand manufacturers' data sheets describing digital and analog electronic circuit elements and DC motors
4. Ability to breadboard, test and troubleshoot practical digital and analog circuits in the laboratory using standard electronics lab instruments and tools.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 State Machine Demonstration ** Yes 10.00 Week 6 3, 4,
2 Analog Interface Demonstration ** Yes 15.00 Week 9 1, 3, 4,
3 Major Project ** Yes 25.00 Week 13 2, 4,
4 Final Exam * No 50.00 Exam Period 1, 2, 3, 4,
Assessment Description: * Need to pass the final exam: You need to get at least 50% in the final exam to pass the unit of study, regardless of the sum of your individual marks. Failing the final exam will result in a maximum final mark of 47.

The final exam will cover all aspects of the unit of study

** Lab assignment 1,2 and 3 must be demonstrated on the due day. The assessment task must be repeated if the student misses it due to special consideration. A design report will be required to be presented on the day of the demonstration.

Late submission will be penalised 20% of the maximum mark for the assignment per day (or part thereof) that it is late.

There may be statistically defensible moderation when combining the marks from each component to ensure consistency of marking between markers, and alignment of final grades with unit outcomes
Grading:
Grade Type Description
Standards Based Assessment Final grades in this unit are awarded at levels of HD for High Distinction, DI (previously D) for Distinction, CR for Credit, PS (previously P) for Pass and FA (previously F) for Fail as defined by University of Sydney Assessment Policy. Details of the Assessment Policy are available on the Policies website at http://sydney.edu.au/policies . Standards for grades in individual assessment tasks and the summative method for obtaining a final mark in the unit will be set out in a marking guide supplied by the unit coordinator.
Policies & Procedures: See the FEIT Faculty Policies & Procedures page on Canvas at https://canvas.sydney.edu.au/courses/2806/pages/feit-faculty-policies-and-procedures for information regarding University policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.
Recommended Reference/s: Note: References are provided for guidance purposes only. Students are advised to consult these books in the university library. Purchase is not required.

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Lecture: Intro to Mechatronic Design; Basic electronics
Week 2 Lab: Basic electrical measurements
Intro to breadboards and prototyping, Signals and their representation
Week 3 Lab: Conversion between bases. Generation of signals
Logic 1 - Components for logic Logic 2 - Intro to logic functions
Week 4 Lab: Practical logic design
Lecture: Simplifying truth tables More simplification
Week 5 Lecture: Visualising logic tables and Karnaugh Maps Storing Information
Lab: Minterms, Maxterms
Week 6 Lab: Karnaugh Maps
Lecture: Sequential Logic State Machines
Assessment Due: State Machine Demonstration **
Week 7 Lecture: Real Circuits 1 Interfaces 1
Lab: State Machine 1
Week 8 Lecture: Interfaces 2 Real Circuits 2
Lab: State Machine 2
Week 9 Lecture: Op Amp 1 Op Amp 2
Lab: State Machine 3
Assessment Due: Analog Interface Demonstration **
Week 10 Lab: DC Motor Lab 1
Lecture: Brushless DC Motors Transistors as Switches (PWM)
Week 11 Lecture: Motor Configurations (and datasheets) Feedback Control
Lab: DC Motor Lab 2
Week 12 Lab: DC Motor Lab 3
Lecture: Power Supplies Analogue to Digital (and back)
Week 13 Lecture: Review - Digital Review - Analog
Assessment Due: Major Project **
Exam Period Assessment Due: Final Exam *

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Mechatronic Mid-Year 2016, 2017, 2018, 2019, 2020
Mechatronic/ Project Management 2019, 2020
Mechatronic 2016, 2017, 2018, 2019, 2020
Mechatronic / Arts 2016, 2017, 2018, 2019, 2020
Mechatronic / Commerce 2016, 2017, 2018, 2019, 2020
Mechatronic / Medical Science 2016, 2017
Mechatronic / Music Studies 2016, 2017
Mechatronic / Project Management 2016, 2017, 2018
Mechatronic / Science 2016, 2017, 2018, 2019, 2020
Mechatronic/Science (Health) 2018, 2019, 2020
Mechatronic / Law 2016, 2017, 2018, 2019, 2020
Mechatronic/Science (Medical Science Stream) 2018, 2019, 2020
Biomedical Mid-Year 2016, 2017, 2018, 2019, 2020
Biomedical 2016, 2017, 2018, 2019, 2020

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
(5) Interdisciplinary, Inclusiveness, Influence (Level 2) No 0%
(4) Design (Level 2) No 51.25%
(3) Problem Solving and Inventiveness (Level 2) No 0%
(2) Engineering/ IT Specialisation (Level 2) No 48.75%

These goals are selected from Engineering & IT Graduate Outcomes Table 2018 which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table 2018 for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.