Note: This unit version is currently under review and is subject to change!

ELEC3608: Computer Architecture (2019 - Semester 2)

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Unit: ELEC3608: Computer Architecture (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Senior
Faculty/School: School of Electrical & Information Engineering
Unit Coordinator/s: Prof Leong, Philip
Session options: Semester 2
Versions for this Unit:
Campus: Camperdown/Darlington
Pre-Requisites: ELEC2602. Knowledge of digital logic (logic operations, theorems and Boolean algebra, number systems, combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, design of a simple computer, and using hardware description languages such as VHDL or Verilog) is required.
Brief Handbook Description: This unit of study explores the design of a computer system at the architectural and digital logic level. Topics covered include instruction sets, computer arithmetic, performance evaluation, datapath design, pipelining, memory hierarchies including caches and virtual memory, I/O devices, and bus-based I/O systems. Students will design a pipelined reduced instruction set processor.
Assumed Knowledge: ELEC3607. Knowledge of microprocessor systems (embedded systems architecture, design methodology, interfacing and programming) is required.
Timetable: ELEC3608 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 2.00 1 12
2 Tutorial 2.00 1 12
3 Project Work - own time 4.00 1 3
T&L Activities: Laboratory: Laboratory experiments to revise concepts and gain familiarity with design tools.

Tutorial: Reinforce concepts and provide design examples of materials covered in lectures.

Independent Study: Self study

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

(6) Communication and Inquiry/ Research (Level 2)
1. Understand the literature in computer architecture design.
2. Develop their communication skills through the assignment.
(7) Project and Team Skills (Level 2)
3. Work in teams through assignments and deal with project managements issues of completing a design exercise.
(8) Professional Effectiveness and Ethical Conduct (Level 2)
4. Students will learn how economic issues affect computer designers.
(4) Design (Level 3)
5. Design a pipelined RISC processor with memory hierarchy.
(2) Engineering/ IT Specialisation (Level 3)
6. Critically evaluate different pipelining schemes, memory designs and instruction sets.
(1) Maths/ Science Methods and Tools (Level 3)
7. Model and benchmark the performance of different computer architectures.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Tutorial 1 Yes 2.00 Week 3 4, 5, 6,
2 Tutorial 2 Yes 2.00 Week 4 1, 5, 6, 7,
3 Tutorial 3 Yes 2.00 Week 5 1, 5, 6, 7,
4 Tutorial 4 Yes 2.00 Week 6 1, 5, 6, 7,
5 Tutorial 5 Yes 2.00 Week 7 1, 5, 6, 7,
6 Design exercise Yes 30.00 Week 12 2, 3, 5, 6,
7 Final exam No 60.00 Exam Period 1, 5, 6, 7,
Assessment Description: Tutorials: Cover basic theory for course.

Assignment: Design project.

Final Exam: 2 hour closed book.
Grading:
Grade Type Description
Standards Based Assessment Final grades in this unit are awarded at levels of HD for High Distinction, DI (previously D) for Distinction, CR for Credit, PS (previously P) for Pass and FA (previously F) for Fail as defined by University of Sydney Assessment Policy. Details of the Assessment Policy are available on the Policies website at http://sydney.edu.au/policies . Standards for grades in individual assessment tasks and the summative method for obtaining a final mark in the unit will be set out in a marking guide supplied by the unit coordinator.
Policies & Procedures: See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.
Prescribed Text/s: Note: Students are expected to have a personal copy of all books listed.

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Lecture: Computer abstractions and technology
Week 2 Lecture/Tutorial: Instruction sets
Week 3 Lecture/Tutorial: Computer arithmetic
Assessment Due: Tutorial 1
Week 4 Lecture/Tutorial: Computer arithmetic
Assessment Due: Tutorial 2
Week 5 Lecture/Tutorial: Processor design
Assessment Due: Tutorial 3
Week 6 Lecture/Tutorial: Processor design
Assessment Due: Tutorial 4
Week 7 Lecture/Tutorial: Processor design (pipelining)
Assessment Due: Tutorial 5
Week 8 Lecture/Tutorial: Processor design (pipelining)
Week 9 Lecture/Tutorial: Memory hierarchy
Week 10 Lecture/Tutorial: Memory hierarchy
Week 11 Lecture/Tutorial: Storage and I/O
Week 12 Storage and I/O
Assessment Due: Design exercise
Week 13 Lecture/Tutorial: Multicores, Multiprocessors and Clusters
Exam Period Assessment Due: Final exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Electrical (Computer) (till 2014) 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Arts 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Commerce 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Medical Science 2011, 2013, 2014
Electrical Engineering (Computer) / Science 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Law 2013, 2014
Electrical (Computer) 2015
Electrical (Computer) / Arts 2015
Electrical (Computer) / Commerce 2015
Electrical (Computer) / Medical Science 2015
Electrical (Computer) / Project Management 2015
Electrical (Computer) / Science 2015
Electrical (Computer) / Law 2015
Electrical (till 2014) 2011, 2012, 2013, 2014
Electrical Engineering / Arts 2011, 2012, 2013, 2014
Electrical Engineering / Commerce 2010, 2011, 2012, 2013, 2014
Electrical Engineering (Bioelectronics) / Arts 2011, 2012
Electrical Engineering (Bioelectronics) / Science 2011, 2012
Electrical Engineering / Medical Science 2011, 2012, 2013, 2014
Electrical Engineering / Project Management 2012, 2013, 2014
Electrical Engineering / Science 2011, 2012, 2013, 2014
Electrical (Power) (till 2014) 2014
Electrical Engineering (Power) / Project Management 2012, 2013, 2014
Electrical (Telecommunications) (till 2014) 2012, 2013, 2014
Electrical Engineering (Telecommunications) / Science 2011, 2012, 2013, 2014
Biomedical Mid-Year 2016, 2017, 2018, 2019, 2020
Biomedical 2016, 2017, 2018, 2019, 2020
Electrical Mid-Year 2016, 2017, 2018, 2019, 2020
Electrical/ Project Management 2019, 2020
Electrical 2015, 2016, 2017, 2018, 2019, 2020
Electrical / Arts 2016, 2017, 2018, 2019, 2020
Electrical / Commerce 2016, 2017, 2018, 2019, 2020
Electrical / Medical Science 2016, 2017
Electrical / Music Studies 2016, 2017
Electrical / Project Management 2016, 2017, 2018, 2020
Electrical / Science 2016, 2017, 2018, 2019, 2020
Electrical/Science (Health) 2018, 2019, 2020
Electrical / Law 2016, 2017, 2018, 2019, 2020
Electrical (Power) 2015
Electrical (Telecommunications) 2015
Software Mid-Year 2016, 2017, 2018, 2019, 2020
Software/ Project Management 2019, 2020
Software 2015, 2016, 2017, 2018, 2019, 2020
Software / Arts 2016, 2017, 2018, 2019, 2020
Software / Commerce 2016, 2017, 2018, 2019, 2020
Software / Medical Science 2016, 2017
Software / Music Studies 2016, 2017
Software / Project Management 2016, 2017, 2018
Software / Science 2016, 2017, 2018, 2019, 2020
Software/Science (Health) 2018, 2019, 2020
Software / Law 2016, 2017, 2018, 2019, 2020
Electrical/Science (Medical Science Stream) 2018, 2019, 2020
Software/Science (Medical Science Stream) 2018, 2019, 2020
Electrical Engineering (Telecommunications) / Arts 2011, 2012, 2013, 2014
Electrical Engineering (Telecommunications) / Medical Science 2011, 2012, 2013, 2014

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
(6) Communication and Inquiry/ Research (Level 2) No 22.6%
(7) Project and Team Skills (Level 2) No 9%
(8) Professional Effectiveness and Ethical Conduct (Level 2) No 0.4%
(5) Interdisciplinary, Inclusiveness, Influence (Level 3) No 0%
(4) Design (Level 3) No 24.2%
(2) Engineering/ IT Specialisation (Level 3) No 27.2%
(3) Problem Solving and Inventiveness (Level 3) No 0%
(1) Maths/ Science Methods and Tools (Level 3) No 16.6%

These goals are selected from Engineering & IT Graduate Outcomes Table 2018 which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table 2018 for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.