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ELEC9607: Embedded Systems (2019 - Semester 1)

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Unit: ELEC9607: Embedded Systems (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Postgraduate
Faculty/School: School of Electrical & Information Engineering
Unit Coordinator/s: Dr Boland, David
Session options: Semester 1
Versions for this Unit:
Site(s) for this Unit: http://www.eelab.usyd.edu.au/ELEC3607/index.html
Campus: Camperdown/Darlington
Pre-Requisites: None.
Prohibitions: ELEC5741.
Brief Handbook Description: The aim of this unit of study is to teach students about microprocessors and their use. This includes architecture, programming and interfacing of microcomputers, peripheral devices and chips, data acquisition, device monitoring and control and communications.
Assumed Knowledge: Logic operations, theorems and Boolean algebra, data representation, number operations (binary, hex, integers and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, basic computer organisation, the CPU, peripheral devices, software organisation, machine language, assembly language, operating systems, data communications and computer networks.
Lecturer/s: Dr Flower, Barry
Timetable: ELEC9607 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 1.00 1 13
2 Laboratory 3.00 1 10
3 Independent Study 8.00 1 13
T&L Activities: Laboratory: Laboratory exercises to re-enforce theory.

Independent Study: Reading of text.

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

(6) Communication and Inquiry/ Research (Level 2)
1. Ability to maintain professional records and documentation of the work performed by keeping a laboratory log book with specific information on problem solving activities.
(7) Project and Team Skills (Level 2)
2. Ability to work in a team by participating and engaging constructively with other team members, drawing on their specific knowledge and abilities, and encouraging group dynamics and harmony in solving specific engineering problems.
(4) Design (Level 3)
3. Ability to solve problems by undertaking investigation and solution formulation and then using a clearly defined approach for specific microcomputer problems.
(2) Engineering/ IT Specialisation (Level 3)
4. Demonstrable understanding of the tenets and concepts of the microcomputer.
5. Capacity to apply microcomputer concepts, principles and techniques to various engineering specific applications, to the extent of the material presented throughout the course.
6. Ability to demonstrate an understanding of microprocessor data sheets by identifying their structure and format and gauging the context of their data.
7. Ability to demonstrate an understanding of the concepts in digital systems fundamentals.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Labs Yes 10.00 Multiple Weeks 1, 2, 3, 5,
2 Assignment Yes 20.00 Week 13 1, 2, 3, 4, 5, 6, 7,
3 Final Exam No 70.00 Exam Period 4, 5, 6, 7,
Assessment Description: Final Exam: 2 hour, multiple-choice exam.

Log Book: Log book kept on each laboratory exercise.

Assignment: Complete the design and implementation of an embedded system of the students` choosing.
Grading:
Grade Type Description
Standards Based Assessment Final grades in this unit are awarded at levels of HD for High Distinction, DI (previously D) for Distinction, CR for Credit, PS (previously P) for Pass and FA (previously F) for Fail as defined by University of Sydney Assessment Policy. Details of the Assessment Policy are available on the Policies website at http://sydney.edu.au/policies . Standards for grades in individual assessment tasks and the summative method for obtaining a final mark in the unit will be set out in a marking guide supplied by the unit coordinator.
Policies & Procedures: See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Independent study.
Introduction.
Week 2 Independent study.
Assembly language I.
Laboratory exercise 1.
Week 3 Assembly language II.
Laboratory exercise 2.
Independent study.
Week 4 General purpose I/O.
Independent study.
Laboratory exercise 3.
Week 5 Laboratory exercise 4.
Timers and counters.
Independent study.
Week 6 Laboratory exercise 5.
Interrupts.
Independent study.
Week 7 Assignment 1.
Serial interfaces.
Independent study.
Week 8 Bus interfaces.
Assignment 2.
Independent study.
Week 9 Debugging.
Assignment 3.
Independent study.
Week 10 Assignment 4.
Operating systems.
Independent study.
Week 11 Assignment 5.
Real-time issues.
Independent study.
Week 12 Assignment 6.
Multiprocessor systems.
Independent study.
Week 13 Independent study.
Review.
Assessment Due: Assignment
STUVAC (Week 14) Independent study.
Exam Period Final exam.
Assessment Due: Final Exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Master of Professional Engineering (Accelerated) (Intelligent Information Engineering) 2020
Master of Professional Engineering (Intelligent Information Engineering) 2020
Master of Professional Engineering (Accelerated) (Electrical) 2019, 2020
Master of Professional Engineering (Electrical) 2015, 2016, 2017, 2018, 2019, 2020

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
(6) Communication and Inquiry/ Research (Level 2) No 4.5%
(7) Project and Team Skills (Level 2) No 6.5%
(8) Professional Effectiveness and Ethical Conduct (Level 1) No 0%
(5) Interdisciplinary, Inclusiveness, Influence (Level 3) No 0%
(4) Design (Level 3) No 5.5%
(2) Engineering/ IT Specialisation (Level 3) No 83.5%
(3) Problem Solving and Inventiveness (Level 3) No 0%
(1) Maths/ Science Methods and Tools (Level 3) No 0%

These goals are selected from Engineering & IT Graduate Outcomes Table 2018 which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table 2018 for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.