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ELEC9608: Computer Architecture (2019 - Semester 2)

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Unit: ELEC9608: Computer Architecture (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Postgraduate
Faculty/School: School of Electrical & Information Engineering
Unit Coordinator/s: Prof Leong, Philip
Session options: Semester 2
Versions for this Unit:
Campus: Camperdown/Darlington
Pre-Requisites: ELEC9602. Knowledge of digital logic (logic operations, theorems and Boolean algebra, number systems, combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, design of a simple computer, and using hardware description languages such as VHDL or Verilog) is required.
Prohibitions: ELEC3608.
Brief Handbook Description: This unit of study explores the design of a computer system at the architectural and digital logic level. Topics covered include instruction sets, computer arithmetic, performance evaluation, datapath design, pipelining, memory hierarchies including caches and virtual memory, I/O devices, and bus-based I/O systems. Students will design a pipelined reduced instruction set processor.
Assumed Knowledge: ELEC9607. Knowledge of microprocessor systems (embedded systems architecture, design methodology, interfacing and programming) is required.
Timetable: ELEC9608 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 2.00 1 12
2 Tutorial 2.00 1 12
3 Project Work - own time 4.00 1 3
T&L Activities: Laboratory: Laboratory experiments to revise concepts and gain familiarity with design tools.

Tutorial: Reinforce concepts and provide design examples of materials covered in lectures.

Independent Study: Self study

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

Unassigned Outcomes
1. Students will understand how to design a pipelined RISC processor with memory hierarchy.
2. Students will be able to critically evaluate different pipelining schemes, memory designs and instruction sets.
3. Students will be able to model and benchmark the performance of different computer architectures.
4. Students will be able to understand the literature in computer architecture design.
5. Students will further develop their communication skills through the assignment.
6. Students will learn how economic issues affect computer designers.
7. Students will be given the opportunity to work in teams through assignments and deal with project managements issues of completing a design exercise.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Tutorial 1 Yes 2.00 Week 3 1, 2, 6,
2 Tutorial 2 Yes 2.00 Week 4 1, 2, 3, 4,
3 Tutorial 3 Yes 2.00 Week 5 1, 2, 3, 4,
4 Tutorial 4 Yes 2.00 Week 6 1, 2, 3, 4,
5 Tutorial 5 Yes 2.00 Week 7 1, 2, 3, 4,
6 Design exercise Yes 30.00 Week 12 1, 2, 5, 7,
7 Final exam No 60.00 Exam Period 1, 2, 3, 4,
Assessment Description: Tutorials: Cover basic theory for course.

Assignment: Design project.

Final Exam: 2 hour closed book.
Policies & Procedures: See the policies page of the faculty website at http://sydney.edu.au/engineering/student-policies/ for information regarding university policies and local provisions and procedures within the Faculty of Engineering and Information Technologies.
Prescribed Text/s: Note: Students are expected to have a personal copy of all books listed.

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Lecture: Computer abstractions and technology
Week 2 Lecture/Tutorial: Instruction sets
Week 3 Lecture/Tutorial: Computer arithmetic
Assessment Due: Tutorial 1
Week 4 Lecture/Tutorial: Computer arithmetic
Assessment Due: Tutorial 2
Week 5 Lecture/Tutorial: Processor design
Assessment Due: Tutorial 3
Week 6 Lecture/Tutorial: Processor design
Assessment Due: Tutorial 4
Week 7 Lecture/Tutorial: Processor design (pipelining)
Assessment Due: Tutorial 5
Week 8 Lecture/Tutorial: Processor design (pipelining)
Week 9 Lecture/Tutorial: Memory hierarchy
Week 10 Lecture/Tutorial: Memory hierarchy
Week 11 Lecture/Tutorial: Storage and I/O
Week 12 Storage and I/O
Assessment Due: Design exercise
Week 13 Lecture/Tutorial: Multicores, Multiprocessors and Clusters
Exam Period Assessment Due: Final exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Master of Professional Engineering (Accelerated) (Electrical) 2019, 2020
Master of Professional Engineering (Electrical) 2017, 2018, 2019, 2020

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
(6) Communication and Inquiry/ Research (Level 2) No 0%
(7) Project and Team Skills (Level 2) No 0%
(8) Professional Effectiveness and Ethical Conduct (Level 2) No 0%
(5) Interdisciplinary, Inclusiveness, Influence (Level 3) No 0%
(4) Design (Level 3) No 0%
(2) Engineering/ IT Specialisation (Level 3) No 0%
(3) Problem Solving and Inventiveness (Level 3) No 0%
(1) Maths/ Science Methods and Tools (Level 3) No 0%

These goals are selected from Engineering & IT Graduate Outcomes Table 2018 which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table 2018 for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.