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ELEC4605: Computer Architecture (2010 - Semester 1)

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Unit: ELEC4605: Computer Architecture (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Senior Advanced
Faculty/School: School of Electrical & Information Engineering
Unit Coordinator/s: Dr Rathmell, James
Session options: Semester 1
Versions for this Unit:
Site(s) for this Unit: http://www.ee.usyd.edu.au/~jimr/teach/elec4605/index.html
Campus: Camperdown/Darlington
Pre-Requisites: ELEC1601 AND ELEC2602 AND ELEC3607.
Brief Handbook Description: The digital systems design process. The design cycle. Top down design. Specification. Functional design. Structural design. Testing. Hardware description languages such as Verilog or VHDL. Digital systems architectures. Processors, buses and I/O devices. Synchronous, asynchronous and semi-synchronous buses. Bus interconnections. Memory and I/O interface design. Static and dynamic memory design. Memory interfacing. Interrupts. Vectored interrupts. Interrupt controllers. Parallel interface design. Serial interface design. Bus arbitration. Processor interfacing. IBM PC interfacing. PCB and packaging design, grounding, shielding and power distribution, some case studies.
Assumed Knowledge: ELEC1601 AND ELEC2602. Logic operations, theorems and Boolean algebra, data representation, number operations (binary, hex, integers and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, basic computer organisation, the CPU, peripheral devices, software organisation, machine language, assembly language, operating systems, data communications and computer networks, microprocessors and their use, the architecture, programming and interfacing of microcomputers, peripheral devices and chips, data acquisition, device monitoring and control and other communications.
Lecturer/s: Dr Rathmell, James
Timetable: ELEC4605 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Independent Study 8.00 1 13
2 Laboratory 3.00 1 10
3 Lecture 1.00 1 13
T&L Activities: Laboratory: Laboratory exercises to re-enforce theory.

Lecture: lectures on theory.

Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.

Attribute Development Method Attribute Developed
Laboratory exercises consist of advanced design and problem solving. Design and Problem Solving Skills (Level 4)
Expertise specific to computers and advanced digital systems. Discipline Specific Expertise (Level 5)
Development of advanced fundamentals of computers and projects. Fundamentals of Science and Engineering (Level 3)
Skill in accessing and handling information on computers. Information Skills (Level 2)
Working in groups to solve design problems. Professional Communication (Level 2)
Development of professional practice in design projects. Professional Values, Judgement and Conduct (Level 2)
Working in teams on design projects. Teamwork and Project Management (Level 2)

For explanation of attributes and levels see Engineering/IT Graduate Attribute Matrix 2009.

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

Design and Problem Solving Skills (Level 4)
1. Proficiency in creatively applying concepts and principles developed in the course to solve advanced problems in computers.
Discipline Specific Expertise (Level 5)
2. Demonstrable ability to apply concepts, principles and techniques of computer systems to specific computer applications.
3. Ability to illustrate an understanding of FPGA and design system data sheets by identifying their content and applicability to particular computer engineering systems.
Fundamentals of Science and Engineering (Level 3)
4. Ability to demonstrate an understanding of fundamental computer engineering concepts and knowledge to the extent of the material presented.
Professional Communication (Level 2)
5. Ability to write and maintain a laboratory log book to communicate problem-solving activities by using clear and concise language, sketches and diagrams at a technical level fitting for the tasks performed.
Professional Values, Judgement and Conduct (Level 2)
6. The ability to conduct an advanced design project as a hardware/software co-design in an FPGA
Teamwork and Project Management (Level 2)
7. Ability to contribute to team work by assuming roles and responsibilities, showing initiative and being receptive to alternate viewpoints with a constructive approach towards reaching a consensus on the solution to assigned problems.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Final Exam No 90.00 Exam Period 2, 3, 4,
2 Log Book Yes 10.00 Multiple Weeks 1, 2, 5, 6, 7,
Assessment Description: Final Exam: 2 hour, multiple-choice exam.

Log Book: Log book kept on each of 10 laboratory exercises.
Grading:
Grade Type Description
Standards Based Assessment Final grades in this unit are awarded at levels of HD for High Distinction, DI (previously D) for Distinction, CR for Credit, PS (previously P) for Pass and FA (previously F) for Fail as defined by University of Sydney Assessment Policy. Details of the Assessment Policy are available on the Policies website at http://sydney.edu.au/policies . Standards for grades in individual assessment tasks and the summative method for obtaining a final mark in the unit will be set out in a marking guide supplied by the unit coordinator.
Policies & Procedures: The faculty attempts to maintain consistency and quality in its T&L operations by adhering to Academic Board policy. These policies can be found on the Central Policy Online site. A brief summary of the relevant T&L policies that should be referred to while filling in these forms can be found at the Faculty of Engineering and Information Technologies Policy Page.
Online Course Content: http://www.ee.usyd.edu.au/~jimr/teach/elec4605/index.html
Note on Resources: Comprehensive lecture and reference notes, available on-line and for purchase.

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Welcome and Hardware Description Languages.
Independent study.
Week 2 VHDL Design and Design Verification.
Independent study.
Week 3 Independent study.
Computer Components (Memory and I/O).
Week 4 Laboratory Tutorial exercise 1.
Independent study.
Computer Architectures (Bus Types and Memory Map).
Week 5 Laboratory Tutorial exercise 2.
Independent study.
Systems Engineering.
Week 6 Laboratory Tutorial exercise 3.
Independent study.
Laboratory Introduction.
Week 7 Laboratory Tutorial exercise 4.
Independent study.
Digital Systems Design.
Week 8 Independent study.
Computer Interfacing.
Laboratory Tutorial exercise 5.
Week 9 Independent study.
Laboratory Design exercise 1.
ISA Bus.
Week 10 PCI Bus.
Independent study.
Laboratory Design exercise 2.
Week 11 Laboratory Design exercise 3.
Independent study.
Wishbone Interconnection Architecture.
Week 12 Laboratory Design exercise 4.
Independent study.
Universal Serial Bus.
Week 13 Laboratory Design exercise 5.
Independent study.
Unit of Study Review.
STUVAC (Week 14) Independent study.
Exam Period Final exam.
Assessment Due: Final Exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Computer Engineering (till 2010) 2010
Computer Engineering / Commerce 2010
Electrical Engineering (Computer) / Law 2011, 2012
Electrical (till 2014) 2010, 2011, 2012, 2013
Electrical Engineering / Arts 2011, 2012, 2013, 2014
Electrical Engineering / Commerce 2010, 2011, 2012, 2013, 2014
Electrical (Bioelectronics) (till 2012) 2011, 2012
Electrical Engineering (Bioelectronics) / Arts 2011, 2012
Electrical Engineering (Bioelectronics) / Science 2011, 2012
Electrical Engineering / Medical Science 2011, 2012, 2013, 2014
Electrical Engineering / Project Management 2012, 2013, 2014
Electrical Engineering / Science 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Arts 2011, 2012, 2013, 2014
Electrical Engineering (Computer) / Science 2011, 2012, 2013, 2014
Electrical (Power) (till 2014) 2010, 2011, 2012, 2013
Electrical Engineering (Power) / Arts 2011, 2012, 2013, 2014
Electrical Engineering (Power) / Project Management 2012, 2013, 2014
Electrical Engineering (Power) / Science 2011, 2012, 2013, 2014
Electrical (Telecommunications) (till 2014) 2011, 2012, 2013
Electrical Engineering (Telecommunications) / Science 2011, 2012, 2013, 2014
Software Engineering (till 2014) 2010, 2011, 2012, 2013, 2014
Software Engineering / Arts 2011, 2012, 2013, 2014
Software Engineering / Commerce 2010, 2011, 2012, 2013, 2014
Software Engineering / Medical Science 2011, 2012, 2013, 2014
Software Engineering / Project Management 2012, 2013, 2014
Software Engineering / Science 2011, 2012, 2013, 2014
Telecommunications (till 2010) 2010
Bachelor of Information Technology (Computer Science) 2014 and earlier 2009, 2010, 2011
Bachelor of Information Technology (Information Systems) 2014 and earlier 2010, 2011, 2012
Information Technology (Information Systems) / Commerce 2012
Electrical Engineering (Computer) / Medical Science 2011, 2013, 2014
Electrical Engineering (Telecommunications) / Arts 2011, 2012, 2013, 2014
Electrical Engineering (Telecommunications) / Medical Science 2011, 2012, 2013, 2014

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
Design and Problem Solving Skills (Level 4) Yes 2%
Discipline Specific Expertise (Level 5) Yes 61.99%
Fundamentals of Science and Engineering (Level 3) Yes 30%
Information Skills (Level 2) Yes 0%
Professional Communication (Level 2) Yes 2%
Professional Values, Judgement and Conduct (Level 2) Yes 2%
Teamwork and Project Management (Level 2) Yes 2%

These goals are selected from Engineering/IT Graduate Attribute Matrix 2009 which defines overall goals for courses where this unit is primarily offered. See Engineering/IT Graduate Attribute Matrix 2009 for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.