Note: This unit is an archived version! See Overview tab for delivered versions.
ELEC5402: Digital Integrated Circuit Design (2011 - Semester 1)
Unit: | ELEC5402: Digital Integrated Circuit Design (6 CP) |
Mode: | Normal-Day |
On Offer: | Yes |
Level: | Postgraduate |
Faculty/School: | School of Electrical & Computer Engineering |
Unit Coordinator/s: |
Dr McEwan, Alistair
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Session options: | Semester 1 |
Versions for this Unit: | |
Site(s) for this Unit: |
http://www.eelab.usyd.edu.au/ELEC5402 |
Campus: | Camperdown/Darlington |
Pre-Requisites: | None. |
Brief Handbook Description: | This unit of study explores CMOS technology and integrated circuit design and fabrication. The fundamental theory and techniques behind digital integrated circuit design are introduced. A primary focus of this unit is providing the student with practical laboratory design experience using a professional VLSI CAD tool to design digital integrated circuits. This unit provides a foundation for more advanced digital integrated circuit design techniques and also analogue integrated circuit design. Topics covered in this unit are: IC manufacturing process and CMOS technology, CMOS static logic design, CMOS dynamic logic design, arithmetic building block design, sequential logic design, VLSI interconnection and wiring issues, timing issues, digital memory design, digital system design methodologies. |
Assumed Knowledge: | Electronic circuit design and physics of electronic devices. |
Lecturer/s: |
Dr McEwan, Alistair
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Timetable: | ELEC5402 Timetable | ||||||||||||||||||||
Time Commitment: |
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T&L Activities: | Project Work - in class: Large project assignments in pairs or own work to develop digital integrated circuit designs. Students learn how to use leading IC design software from schematic entry to layout and extracted simulation. Independent Study: Students are required to research and complete assignment work on their own or in small groups. |
Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.
Attribute Development Method | Attribute Developed |
Develop and ability to design digital integrated circuits using advanced design tools and simulation. | Design and Problem Solving Skills (Level 4) |
Understand the foundations of modern CMOS digital IC design. | Discipline Specific Expertise (Level 5) |
An appreciation of the various forms of literature on circuits and systems including technical books and reports, research articles, customer requirements and industry standards. These attributes are acquired through the project work and laboratory/tutorials. | Information Skills (Level 2) |
Ability to explain and build on an understanding of the devices used in integrated circuits. | Professional Communication (Level 2) |
The costs associated with integrated circuits are demand a professional design approach and students study associated issues to ensure reliability and yield. | Professional Values, Judgement and Conduct (Level 2) |
Group interaction in the laboratory and lectures to tackle testing design challenges | Teamwork and Project Management (Level 2) |
For explanation of attributes and levels see Engineering/IT Graduate Attribute Matrix 2009.
Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.
Design and Problem Solving Skills (Level 4)Assessment Methods: |
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Assessment Description: |
Assignment: Formal reports from the practical laboratory experience using the Mentor Graphics professional VLSI CAD tool to design digital integrated circuits. Assessment will include technical description and writing skills in individual reports and participation in group work. Final Exam: The final exam covers all materials presented in the lectures and laboratory. |
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Assessment Feedback: | Lab work will be assessed on a regular basis and feedback given in written and oral form in labs and lectures. Exam preparation including practice quizzes will occur in lectures. | ||||||||||||||||||||||||||||||||||||
Grading: |
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Policies & Procedures: | Policies regarding academic honesty and plagiarism, special consideration and appeals in the Faculty of Engineering and Information Technologies can be found on the Faculty's policy page at http://www.eng.usyd.edu.au/policies Faculty policies are governed by Academic Board resolutions whose details can be found on the Central Policy Online site at http://www.usyd.edu.au/policy/ Policies regarding assessment formatting, submission methods, late submission penalties and assessment feedback depend on the unit of study. Details of these policies, where applicable, should be found above with other assessment details. |
Prescribed Text/s: |
Note: Students are expected to have a personal copy of all books listed.
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Library e-Reserve: | Please check the Library e-Reserve site for additional course resources. |
Online Course Content: | http://www.eelab.usyd.edu.au/ELEC5402 and my uni |
Note on Resources: |
Digital Integrated Circuits, Jan Rabaey, A. Chandrakasan, B. Nikolic, Prentice Hall CMOS Digital Integrated Circuits Analysis and design, Sung-Mo Kang, Yusuf Leblebici, 3rd Edition, McGraw Hill Analog VLSI: Circuits and Principles, Shih-Chii Liu et al., The MIT Press |
Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp
Week | Description |
Week 1 | Introduction |
Week 2 | The MOSFET |
Week 3 | Cadence Demonstration |
Week 4 | Layout |
Assessment Due: Lab 1: Cell Design and Verification | |
Week 5 | Sub-micron Transistors |
Week 6 | Logic Gates |
Week 7 | CMOS Latches |
Assessment Due: Lab 2: Datapath Design and Verification | |
Week 8 | Compound Logic gates |
Week 9 | Dynamic Logic |
Week 10 | Adders |
Assessment Due: Lab 3: Controller Design and Verification | |
Week 11 | Project Work |
Week 12 | Interconnect |
Week 13 | Advanced Integrated Circuit Issues |
Assessment Due: Lab 4: Full Chip Assembly | |
Exam Period | Assessment Due: Final Exam |
Course Relations
The following is a list of courses which have added this Unit to their structure.
Course Goals
This unit contributes to the achievement of the following course goals:
Attribute | Practiced | Assessed |
Design and Problem Solving Skills (Level 4) | Yes | 19% |
Discipline Specific Expertise (Level 5) | Yes | 46.5% |
Fundamentals of Science and Engineering (Level 3) | No | 0% |
Information Skills (Level 2) | Yes | 5.25% |
Professional Communication (Level 2) | Yes | 12% |
Professional Values, Judgement and Conduct (Level 2) | Yes | 10.25% |
Teamwork and Project Management (Level 2) | Yes | 7% |
These goals are selected from Engineering/IT Graduate Attribute Matrix 2009 which defines overall goals for courses where this unit is primarily offered. See Engineering/IT Graduate Attribute Matrix 2009 for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.