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ELEC5615: Advanced Computer Architecture (2010 - Semester 1)

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Unit: ELEC5615: Advanced Computer Architecture (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Postgraduate
Faculty/School: School of Electrical & Computer Engineering
Unit Coordinator/s: Prof Leong, Philip
Session options: Semester 1
Versions for this Unit:
Site(s) for this Unit:
Campus: Camperdown/Darlington
Pre-Requisites: None.
Brief Handbook Description: This unit of study is comprised of a selection of topics covering advanced computer architecture, advanced digital engineering and embedded systems. They may be chosen from the following:

Advanced Computer Architecture: Processor organisation, parallelism, scalability, language and application driven architectures, design tools and methodologies.

Advanced Digital Engineering: Advanced hardware description language skills for ASIC and FPGA design; CAD methodologies; designing for low power, high speed, small area, low cost and testability; advanced printed circuit board design, system design exercises.

Advanced Embedded systems: System on chip design and associated hardware description languages and CAD tools; embedded system internetworking; real time design constraints; case studies and laboratory exercises in communications and industrial control applications.
Assumed Knowledge: ELEC4605 Computer Engineering or ELEC4601 Computer Design.
Lecturer/s: Prof Leong, Philip
Timetable: ELEC5615 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 2.00 1 13
2 Project Work - own time 3.00 1 8
3 Laboratory 2.00 1 12
4 Tutorial 1.00 1 7
T&L Activities: Project Work - own time: Large project assignment in groups of 2-3 to design, build and test a complete computer architecture

Laboratory: Learn the tools and techniques for CPU design

Tutorial: Discuss and solve problems associated with computer architecture

Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.

Attribute Development Method Attribute Developed
Develop and ability to design and build computer architectures using advanced design tools and simulation. Design and Problem Solving Skills (Level 4)
Master the architectures of modern computer systems Discipline Specific Expertise (Level 5)
An appreciation of the literature on computer architecture including technical books and reports, research articles, customer requirements and commercial systems. These attributes are acquired through the project work and laboratory/tutorials. Information Skills (Level 4)
Students will present their design work in group aettings Professional Communication (Level 3)
Group interaction in the laboratory and project to tackle testing design challenges Teamwork and Project Management (Level 5)

For explanation of attributes and levels see Engineering/IT Graduate Attribute Matrix 2009.

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

Design and Problem Solving Skills (Level 4)
1. Design, build and test a modern computer CPU
Discipline Specific Expertise (Level 5)
2. Demonstrate the ability to design a modern computer architecture
Information Skills (Level 4)
3. Be familiar with the literature on computer architecture
Professional Communication (Level 3)
4. Present the resultsof design and laboratory work
Teamwork and Project Management (Level 5)
5. Work in a team on a computer architecture project
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Lab Skills No 10.00 Multiple Weeks 1, 2, 4,
2 Project Yes 20.00 Multiple Weeks 1, 3, 4, 5,
3 Final Exam No 70.00 Exam Period 1, 2, 5,
Assessment Description: Lab Skills: Show mastery tools for designing, building and testing a CPU

Project: Project

Final Exam: Final Exam
Grade Type Description
Standards Based Assessment Final grades in this unit are awarded at levels of HD for High Distinction, DI (previously D) for Distinction, CR for Credit, PS (previously P) for Pass and FA (previously F) for Fail as defined by University of Sydney Assessment Policy. Details of the Assessment Policy are available on the Policies website at . Standards for grades in individual assessment tasks and the summative method for obtaining a final mark in the unit will be set out in a marking guide supplied by the unit coordinator.
Policies & Procedures: The faculty attempts to maintain consistency and quality in its T&L operations by adhering to Academic Board policy. These policies can be found on the Central Policy Online site. A brief summary of the relevant T&L policies that should be referred to while filling in these forms can be found at the Faculty of Engineering and Information Technologies Policy Page.
Online Course Content:

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar

Week Description
Week 1 Fundamentals of computer design
Week 2 Instruction level parallelism
Week 3 Limits to Instruction level parallelism
Week 4 Multiprocessor architectures and systems
Week 5 The memory hierarchy
Week 6 Storage systems
Week 7 Pipelining details
Week 8 IO systems and channel processors
Week 9 FPGA structures
Week 10 CPU design with FPGAs
Week 11 Reconfigurable architectures
Week 12 Runtime reconfiguration
Week 13 Review
Exam Period Final exam
Assessment Due: Final Exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Electrical Mid-Year 2016, 2017, 2018, 2019, 2020, 2021, 2022
Electrical/ Project Management 2019, 2020
Electrical 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022
Electrical / Arts 2016, 2017, 2018, 2019, 2020
Electrical / Commerce 2016, 2017, 2018, 2019, 2020
Electrical / Medical Science 2016, 2017
Electrical / Music Studies 2016, 2017
Electrical / Project Management 2016, 2017, 2018
Electrical / Science 2016, 2017, 2018, 2019, 2020
Electrical / Science (Health) 2018, 2019, 2020
Electrical (Computer) 2015
Electrical / Law 2016, 2017, 2018, 2019, 2020
Electrical (Power) 2015
Electrical (Telecommunications) 2015
Software Mid-Year 2016, 2017, 2018, 2019
Software/ Project Management 2019
Software 2015, 2016, 2017, 2018, 2019
Software / Arts 2016, 2017, 2018, 2019
Software / Commerce 2016, 2017, 2018, 2019
Software / Medical Science 2016, 2017
Software / Music Studies 2016, 2017
Software / Project Management 2016, 2017, 2018
Software / Science 2016, 2017, 2018, 2019
Software / Science (Health) 2018, 2019
Software / Law 2016, 2017, 2018, 2019
Electrical / Science (Medical Science Stream) 2018, 2019, 2020
Master of Professional Engineering (Electrical) 2010, 2011, 2012, 2013
Master of Professional Engineering (Power) 2013
Master of Professional Engineering (Software) 2010, 2011, 2012, 2013
Software / Science (Medical Science Stream) 2018, 2019

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
Design and Problem Solving Skills (Level 4) Yes 31.66%
Discipline Specific Expertise (Level 5) Yes 26.66%
Information Skills (Level 4) Yes 5%
Professional Communication (Level 3) Yes 8.33%
Teamwork and Project Management (Level 5) Yes 28.33%

These goals are selected from Engineering/IT Graduate Attribute Matrix 2009 which defines overall goals for courses where this unit is primarily offered. See Engineering/IT Graduate Attribute Matrix 2009 for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.