Note: This unit is an archived version! See Overview tab for delivered versions.
ELEC2104: Electronic Devices and Circuits (2012 - Semester 2)
Unit: | ELEC2104: Electronic Devices and Circuits (6 CP) |
Mode: | Normal-Day |
On Offer: | Yes |
Level: | Intermediate |
Faculty/School: | School of Electrical & Computer Engineering |
Unit Coordinator/s: |
Dr Jin, Craig
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Session options: | Semester 2 |
Versions for this Unit: | |
Site(s) for this Unit: |
http://www.eelab.usyd.edu.au/ELEC2104/index.htm |
Campus: | Camperdown/Darlington |
Pre-Requisites: | None. |
Brief Handbook Description: | Modern Electronics has come to be known as microelectronics which refers to the Integrated Circuits (ICs) containing millions of discrete devices. This course introduces some of the basic electronic devices like diodes and different types of transistors. It also aims to introduce students the analysis and design techniques of circuits involving these discrete devices as well as the integrated circuits. Completion of this course is essential to specialize in Electrical, Telecommunication or Computer Engineering stream. The knowledge of ELEC1103 is assumed. |
Assumed Knowledge: | ELEC1103. Ohm`s Law and Kirchoff`s Laws; action of Current and Voltage sources; network analysis and the superposition theorem; Thevenin and Norton equivalent circuits; inductors and capacitors, transient response of RL, RC and RLC circuits; the ability to use power supplies, oscilloscopes, function generators, meters, etc. |
Lecturer/s: |
Dr Jin, Craig
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Timetable: | ELEC2104 Timetable | |||||||||||||||||||||||||
Time Commitment: |
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T&L Activities: | Tutorial: Tutorial assistance provided Laboratory: Laboratory experiments Laboratory: Prelab work Independent Study: Self- study |
Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.
Attribute Development Method | Attribute Developed |
Design problems with given specification as well as with assumed parameters. | Design (Level 2) |
Basic electronics concepts and principles, grounded in circuit theory. | Engineering/IT Specialisation (Level 3) |
Ability to apply circuit theory to modelling of electronic circuits and systems. | Maths/Science Methods and Tools (Level 2) |
Lab procedure and conducting experiments under controlled conditions | Information Seeking (Level 2) |
Ability to explain technical concepts | Communication (Level 2) |
Group work in labs | Professional Conduct (Level 2) |
For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.
Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.
Design (Level 2)Assessment Methods: |
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Assessment Description: |
Lab Work: Six labs + Project Weekly Homework: Circuit problems (Online) Conceptual Review Questions: Review lecture concepts (Online) Mid-Sem Exam: Exam conducted in lecture time Final Exam: Final exam |
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Assessment Feedback: | Tutorial participation and log book feedback will be given by tutors and lab assistants. Quiz feedback will be given on-line. Specific feedback will be given in lectures including exam preparation. | ||||||||||||||||||||||||||||||||||||
Grading: |
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Policies & Procedures: | Academic Honesty in Coursework. All students must submit a cover sheet for all assessment work that declares that the work is original and not plagiarised from the work of others. Coursework assessment and examination policy. The faculty policy is to use standards based assessment for units where grades are returned and criteria based assessment for Pass/Fail only units. Norm referenced assessment will only be used in exceptional circumstances and its use will need to be justified to the Undergraduate Studies Committee. Special consideration for illness or misadventure may be considered when an assessment component is severely affected. This policy gives the details of the information that is required to be submitted along with the appropriate procedures and forms. Special Arrangements for Examination and Assessment. In exceptional circumstances alternate arrangements for exams or assessment can be made. However concessions for outside work arrangements, holidays and travel, sporting and entertainment events will not normally be given. Student Appeals against Academic Decisions. Students have the right to appeal any academic decision made by a school or the faculty. The appeal must follow the appropriate procedure so that a fair hearing is obtained. Note that policies regarding assessment submission, penalties and assessment feedback depend upon the individual unit of study. Details of these policies, where applicable, will be found above with other assessment details in this unit outline. All university policies can be found at http://sydney.edu.au/policy Various request forms for the Faculty of Engineering and IT can be found at http://sydney.edu.au/engineering/forms/ |
Prescribed Text/s: |
Note: Students are expected to have a personal copy of all books listed.
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Recommended Reference/s: |
Note: References are provided for guidance purposes only. Students are advised to consult these books in the university library. Purchase is not required.
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Online Course Content: | http://www.eelab.usyd.edu.au/ELEC2104/index.htm |
Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp
Week | Description |
Week 1 | Amplification:Voltage ,Current and Power gains; |
Ideal Op-Amp | |
The Op-Amp terminals: | |
Classification of Amplifiers | |
Circuit models;Frequency response:Amplifier bandwidth, | |
Nonlinear characteristics and Biasing;Symbol Convention; | |
Amplifier Power Supplies; | |
Week 2 | Inverting configuration, Non-inverting configuration, Examples of Op-Amp circuits, Bistble multivibrator |
Week 3 | Analysis of diode circuits. |
The ideal diode, Terminal characteristics of junction diode, | |
Week 4 | The small signal model and its operation, Zener diode regulator, Rectifier circuits. |
Week 5 | Physical structure and mode of operation, Operation of npn transistor in the active mode, Circuit symbol and conventions, Transistor characteristics, Transistor circuits at DC. |
Week 6 | Transistor as an amplifier, |
BJT - Continued: | |
Small signal equivalent models, | |
Graphical analysis, BJT Circuit design. | |
Week 7 | BJT amplifier configurations, Transistor as a switch, Transistor current source. |
BJT - Continued: | |
Week 8 | Structure and operation of MOSFET, i-v characteristic of enhancement MOSFET, The depletion type MOSFET. |
FET: | |
Week 9 | FET continued: |
MOSFET circuits at DC, MOSFET as an amplifier. | |
Assessment Due: Mid-Sem Exam | |
Week 10 | Structure and operation of JFET |
FET Continued: | |
Week 11 | Differential Amplifier: |
Small signal operation of BJT differential amplifier. | |
The BJT differential pair, | |
Week 12 | Small signal operation of BJT differential amplifier |
Week 13 | (Self Study) Examples, Problems |
Exam Period | Assessment Due: Final Exam |
Course Relations
The following is a list of courses which have added this Unit to their structure.
Course Goals
This unit contributes to the achievement of the following course goals:
Attribute | Practiced | Assessed |
Project and Team Skills (Level 2) | No | 0% |
Design (Level 2) | Yes | 15.72% |
Engineering/IT Specialisation (Level 3) | Yes | 58.9% |
Maths/Science Methods and Tools (Level 2) | Yes | 14.22% |
Information Seeking (Level 2) | Yes | 3.72% |
Communication (Level 2) | Yes | 3.72% |
Professional Conduct (Level 2) | Yes | 3.72% |
These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.